Chiplets and 3D Packaging

For most of the chip industry’s history, “a chip” meant one single, continuous piece of silicon — every transistor on it manufactured together, all at once, on the same wafer. As transistors got harder and more expensive to shrink further (see Moore’s Law and Scaling), engineers found a different way to keep packing more computing power into a product: instead of building one giant chip, build several smaller ones and wire them together so tightly they behave like a single chip anyway. Those smaller pieces are called chiplets, and the technology that connects them is advanced packaging.

The problem with one giant chip

A traditional single-piece (“monolithic”) chip has a hidden cost that gets worse as chips get bigger: manufacturing defects. Every wafer has some number of random microscopic flaws scattered across it. A small chip is likely to avoid all of them; a very large chip covers more area, so it’s statistically far more likely that at least one flaw lands somewhere inside it — and one flaw can ruin the entire chip. This means larger monolithic chips have a lower yield (the percentage of chips on a wafer that come out good), which makes them disproportionately expensive. There’s also a practical size ceiling: lithography machines can only expose a certain maximum area in one pass, physically capping how large a single chip can be.

🧩 Think of it like… LEGO bricks versus a single molded plastic toy. If you drop and crack a large one-piece molded toy, the whole thing is ruined — you have to throw it away and start over. But if the same shape is built out of separate LEGO bricks, a flaw in one brick means you replace just that brick, not the whole model. Chiplets apply that same logic to silicon: build the processor out of several smaller, individually-tested pieces instead of one giant, all-or-nothing piece.

What a chiplet actually is

A chiplet is simply a smaller chip — sometimes handling just one function, like a chunk of processor cores, a memory controller, or input/output circuitry — that’s designed from the start to be combined with other chiplets inside a single finished package. Because each chiplet is smaller, it has a much higher manufacturing yield than an equivalent giant monolithic chip would. Chiplets can even be manufactured on completely different process nodes (see What Does “7nm” Actually Mean?) or at different foundries — a processor’s compute cores might use the newest, most expensive node available, while its I/O circuitry, which doesn’t benefit as much from shrinking, uses an older and cheaper one. This mix-and-match flexibility is one of the biggest economic advantages of the chiplet approach.

Advanced packaging: making separate pieces act as one

Building smaller pieces is only half the story — they then have to be connected together closely enough, with high enough bandwidth and low enough delay, that software running on them can’t easily tell they aren’t one chip. That’s the job of advanced packaging, and it goes well beyond older packaging methods (see Packaging and Testing for the more traditional version). Two techniques matter most:

2.5D packaging with an interposer. Instead of connecting chiplets directly to the circuit board below, they’re placed side by side on top of a shared piece of silicon called an interposer, which is threaded with extremely fine wiring. The interposer acts like a miniature, ultra-high-density circuit board sitting between the chiplets and the rest of the package, letting them exchange data far faster and using far less power than if they had to communicate through the coarser wiring of a normal circuit board.
3D stacking with TSVs. Rather than placing chiplets side by side, this approach stacks them directly on top of one another, connected vertically through Through-Silicon Vias (TSVs) — tiny conductive channels etched straight through a chip’s silicon body, similar in spirit to drilling a shaft through multiple floors of a building to run wiring between them. 3D stacking gives the shortest possible connections between chiplets, but also concentrates heat generation into a smaller physical footprint, which makes cooling a harder problem.

3D: TSV StackingPackage substrate

Chiplet (base)Chiplet (stacked)TSVs run vertically through the silicon

Why this matters going forward

Chiplets and advanced packaging represent a genuine shift in strategy for the entire industry: instead of getting all future performance gains from transistor shrinking alone, a growing share now comes from smarter assembly of multiple pieces. This softens the economic pain of slowing Moore’s Law progress, since it’s often cheaper to combine several smaller high-yield chiplets than to gamble on a single enormous monolithic chip. It also gives chip designers more architectural freedom — mixing process nodes, specializing chiplets for particular tasks, and even sourcing chiplets from different manufacturers within one final product, a flexibility explored further in Foundry, Fabless, and IDM.

This approach isn’t free of trade-offs: connecting separate chiplets, even with advanced packaging, is still generally slower and more power-hungry than wiring within a single monolithic piece of silicon. Chiplets trade a bit of raw interconnect efficiency for better manufacturing yield, cost flexibility, and design modularity.

Key takeaways

Chiplets are smaller chips designed to be combined into one package, instead of manufacturing one giant monolithic chip.
Smaller chips have higher manufacturing yield, since they’re less likely to contain a fatal defect — much like LEGO bricks versus one large molded piece.
2.5D packaging places chiplets side by side on a shared silicon interposer with extremely fine wiring; 3D packaging stacks them vertically, connected through Through-Silicon Vias (TSVs).
Chiplets allow mixing different process nodes and even different manufacturers within a single finished product.
The trade-off is that chiplet-to-chiplet connections are still slower and less power-efficient than wiring inside one continuous piece of silicon.

EUV Lithography