From RTL to GDSII

A modern chip can contain tens of billions of transistors, yet no human ever draws them one by one. Instead, engineers describe what the chip should do, and a long chain of software tools progressively transforms that description into the literal geometric shapes that get etched onto a silicon wafer. That pipeline — from a written description of behavior down to a manufacturing-ready layout file — is the backbone of the entire chip design industry, and it’s usually called the “RTL-to-GDSII flow.”

Starting with an idea, not a drawing

Chip design doesn’t start with wires and transistors. It starts with a specification: what should this chip do, how fast, using how much power, at what cost? An architecture team decides on things like how many processor cores it needs, how much memory it can talk to, and what instructions it must support. This is the blueprint stage — nothing has been “drawn” yet, only decided.

🧩 Think of it like… building a house. You don't start by cutting lumber. You start with a floor plan describing what rooms exist and how they connect. RTL-to-GDSII is the process of turning that floor plan into an exact, buildable construction blueprint — and eventually into the house itself.

Step 1: RTL — describing behavior in code

Engineers write the chip’s logic in a Hardware Description Language (HDL) — almost always Verilog or VHDL — at a level called RTL (Register-Transfer Level). RTL code doesn’t describe transistors; it describes behavior: “on every clock tick, if this condition is true, move this data from register A to register B.” It reads a bit like a programming language, but it actually specifies parallel hardware, not sequential instructions. This connects directly to the ideas in Logic Gates and From Gates to Circuits — RTL is simply a compact, human-writable way to describe huge networks of those same gates and flip-flops.

Step 2: Logic synthesis

RTL code is still abstract — it has to become an actual network of logic gates (AND, OR, NAND, flip-flops, and so on) built from the standard cells a foundry offers. A synthesis tool reads the RTL and automatically generates a “gate-level netlist” — a giant list of gates and the wires connecting them — that implements the same behavior while meeting timing, area, and power targets. This is a bit like a compiler turning source code into machine instructions, except the “machine instructions” here are physical logic gates.

Step 3: Place and route

The netlist now has to become physical geometry. Placement decides where on the chip’s silicon surface each logic gate should physically sit. Routing then draws the actual metal wires connecting all those placed gates together, across many stacked metal layers (see Metallization and Interconnects). Both steps are brutally difficult optimization problems — a modern chip has billions of gates and tens of kilometers of wiring squeezed into a few square centimeters, all while keeping signals fast enough and power consumption low enough.

Step 4: Verification, every step of the way

Verification isn’t a single step at the end — it happens continuously throughout the flow, because a single bug can turn a $20 million mask set into scrap. Engineers check that the design behaves correctly in simulation, that timing is met at every stage, that the physical layout obeys the foundry’s manufacturing rules (Design Rule Checks, or DRC), and that the final layout actually matches the original netlist (Layout Versus Schematic, or LVS). Only after passing these gauntlets does a design move forward.

Step 5: GDSII — the file sent to the fab

The end product of this entire flow is a file in GDSII format (or its modern successor, OASIS) — a database of geometric shapes, layer by layer, describing exactly what should be patterned onto the wafer at every manufacturing step. This file is what gets sent to the foundry, where it drives the photomasks used in Photolithography. GDSII is, in a real sense, the finish line of chip design and the starting line of chip manufacturing.

    flowchart TD
    A["Architecture Spec<br/>(what should it do?)"] --> B["RTL Code<br/>(Verilog / VHDL)"]
    B --> C["Logic Synthesis<br/>(RTL → gate-level netlist)"]
    C --> D["Place & Route<br/>(physical layout of gates + wires)"]
    D --> E["Verification<br/>(timing, DRC, LVS, simulation)"]
    E --> F["GDSII File<br/>(manufacturing-ready layout)"]
    F --> G["Sent to the Foundry"]
    E -.->|"bugs found"| B

Verification isn’t a one-way street — the dotted arrow above is real. Finding a timing violation or a rule check failure often sends engineers back to earlier stages, sometimes all the way back to the RTL, before the flow can continue.

Why this flow exists at all

You might wonder why chips aren’t just designed directly as transistor layouts, the way they were in the earliest decades of the industry. The answer is scale: a chip with a few thousand transistors can be laid out by hand, but a chip with billions cannot. Automating the translation from behavior (RTL) to layout (GDSII) is the only way humans can design at this scale — a topic explored further in EDA Tools, which covers the software that actually performs each of these steps.

Key takeaways

Chip design starts with an architecture spec, then moves to RTL code describing behavior, not transistors.
Logic synthesis turns RTL into a gate-level netlist; place and route turns that netlist into physical geometry.
Verification (timing, DRC, LVS, simulation) runs continuously, not just at the end, because mistakes are extremely expensive to fix after manufacturing begins.
The flow’s final output is a GDSII layout file, which becomes the photomasks used in wafer manufacturing.
This entire automated pipeline exists because modern chips are far too complex — billions of transistors — to design by hand.

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