CMOS Logic

Knowing that a MOSFET is a voltage-controlled switch, and that a logic gate needs to implement a truth table, leaves one big question: how do you actually wire transistors together to make a gate? The answer used in essentially every modern chip is called CMOS — Complementary Metal-Oxide-Semiconductor — and its central trick is pairing up two opposite kinds of transistor so that, in a steady state, current almost never flows straight through the circuit.

Two transistor types, working as a team

CMOS uses two flavors of MOSFET with opposite behavior:

An NMOS transistor turns ON when its gate voltage is HIGH, and acts like a closed switch connecting its terminal toward ground (0V).
A PMOS transistor turns ON when its gate voltage is LOW, and acts like a closed switch connecting its terminal toward the supply voltage (Vdd).

Because they respond oppositely to the same input signal, one is always trying to do the opposite of the other — hence “complementary.”

🧩 Think of it like… a see-saw with two valves, one at the top connected to a water tank (Vdd) and one at the bottom connected to a drain (ground). Push the see-saw one way and the top valve opens while the bottom one seals shut — water flows in, filling the pipe to "full" (logic 1). Push it the other way and the bottom valve opens while the top seals shut — water drains out to "empty" (logic 0). Crucially, the see-saw is built so the two valves are never open at the same time, so water never just gushes straight from tank to drain, wasting energy.

The CMOS inverter

The simplest CMOS gate is the inverter (NOT gate): one PMOS on top acting as a “pull-up” to Vdd, and one NMOS on the bottom acting as a “pull-down” to ground, with both gates tied to the same input and both drains tied together to form the output.

IN = 0 → PMOS on, NMOS off → OUT = 1 | IN = 1 → PMOS off, NMOS on → OUT = 0

Trace through both cases:

Input = 0 (low): The PMOS gate sees a low voltage, so it turns ON, connecting the output to Vdd. The NMOS gate also sees a low voltage, so it turns OFF, disconnecting the output from ground. Output is pulled to Vdd — logic 1.
Input = 1 (high): The PMOS turns OFF (disconnecting Vdd), and the NMOS turns ON (connecting to ground). Output is pulled to ground — logic 0.

In both cases, exactly one transistor is ON and one is OFF — never both ON, never both OFF. That’s the whole trick.

Building a NAND gate

The same pattern extends to more complex gates. A two-input CMOS NAND gate uses two NMOS transistors in series between the output and ground, and two PMOS transistors in parallel between Vdd and the output:

    flowchart TB
    Vdd["Vdd"] --> P1["PMOS A (parallel)"]
    Vdd --> P2["PMOS B (parallel)"]
    P1 --> OUT["OUT"]
    P2 --> OUT
    OUT --> N1["NMOS A"]
    N1 --> N2["NMOS B (series)"]
    N2 --> GND["GND"]

The output only gets pulled down to 0 when both NMOS transistors are ON — meaning both A and B are 1, since a series chain only conducts when every link conducts. If either A or B is 0, at least one PMOS (in the parallel pair) turns ON and pulls the output back up to 1. That’s exactly the NAND truth table from the logic gates page, built directly out of switch topology rather than being “programmed” in any software sense.

Why CMOS barely draws power when idle

This complementary pull-up/pull-down structure is the reason CMOS became the dominant technology for digital chips: in a steady logic state (not switching), one transistor in each pair is always fully OFF, which means essentially no current path exists from Vdd straight down to ground. A MOSFET that’s OFF has an extremely high resistance, so the leftover “leakage” current is tiny (though not exactly zero — leakage is a real concern at the tiny transistor sizes discussed in What Does “7nm” Mean?).

Power is mainly consumed at the moment a gate switches — charging or discharging the tiny capacitance of the output wire:

P_{dynamic} = \alpha \cdot C \cdot V^2 \cdot f

Here $\alpha$ is the fraction of gates switching in a given cycle (activity factor), $C$ is the capacitance being charged or discharged, $V$ is the supply voltage, and $f$ is the clock frequency. This formula is central to chip design: it’s why lowering the supply voltage has an outsized effect on power (it appears squared), and why every chip generation fights to shrink $C$ and $V$ .

Key takeaways

CMOS pairs an NMOS pull-down with a PMOS pull-up, driven by the same input, so exactly one of the two is always ON.
A CMOS inverter is the simplest case; a CMOS NAND gate generalizes it with NMOS in series (pull-down network) and PMOS in parallel (pull-up network).
Because one transistor is always OFF in steady state, CMOS gates draw very little static current — power is dominated by the act of switching, following $P = \alpha C V^2 f$ .
This series/parallel switch-network idea is how every gate from Logic Gates gets physically realized in silicon, and it’s the building block used in From Gates to Circuits.

Logic Gates From Gates to Circuits