From Gates to Circuits

A single logic gate can’t do much on its own — but wire a handful of them together in the right pattern and you get something genuinely useful, like a circuit that adds two numbers. Wire in a feedback loop instead of a straight-through path, and you get something even more surprising: a circuit that can remember a bit after its inputs disappear. This page builds both, and in doing so bridges from “gates” to the beginnings of a real processor.

Building an adder

Suppose you want to add two single-bit numbers, A and B. There are four possible cases: 0+0=0, 0+1=1, 1+0=1, and 1+1=10 (binary two, meaning “0 with a carry of 1” — just like adding 9+1 in decimal, where you write 0 and carry a 1). That’s exactly two outputs: a Sum bit and a Carry bit.

Look closely and you’ll notice Sum is exactly the XOR truth table, and Carry is exactly the AND truth table, both from Logic Gates. So a half-adder is just one XOR gate and one AND gate, sharing the same two inputs:

    flowchart LR
    A["A"] --> XOR["XOR"]
    B["B"] --> XOR
    XOR --> Sum["Sum"]
    A --> AND["AND"]
    B --> AND
    AND --> Carry["Carry"]
  

It’s called a “half” adder because it doesn’t accept a carry-in from a previous column — useful only for the rightmost bit. A full adder accepts a carry-in too (A, B, and Carry-in as three inputs), and can be built from two half-adders plus an OR gate to combine the two possible carry-out signals. Chain enough full adders together, one per bit position, and you have a circuit that adds two full multi-bit binary numbers — the arithmetic core of every processor’s ALU (arithmetic logic unit).

The problem straight-through circuits can’t solve

Everything so far is combinational logic: the output depends only on the current inputs, with no memory of the past. That’s fine for an adder, but a real computer needs to remember things — the contents of a register, the state of a running program — even while inputs are changing elsewhere on the chip. For that, you need sequential logic, and the key trick is feedback: routing a gate’s output back around into its own input.

The latch: the simplest 1-bit memory

The classic example is the SR latch (Set-Reset latch), built from just two NOR gates (or two NAND gates, in a different flavor) cross-coupled so each gate’s output feeds the other gate’s input.

Momentarily pulsing S (Set) to 1 forces the output Q to 1; momentarily pulsing R (Reset) forces Q back to 0. The important part happens when both S and R return to 0: instead of the output going blank or undefined, the loop keeps re-feeding each gate’s last output back into the other gate, so Q holds its value indefinitely. That’s a working 1-bit memory cell — no capacitor, no special material, just two gates and a feedback wire.

Real chips more commonly use a refined version called a D flip-flop, which only updates its stored bit at a precise moment — the edge of a clock signal, a steady square wave ticking at a fixed frequency that keeps every part of the chip synchronized. Instead of “hold whatever value is on the loop right now,” a D flip-flop says “capture the input value only when the clock ticks, and hold it steady until the next tick.” Chaining many flip-flops together, one per bit, builds a register — the small, extremely fast storage that a CPU keeps its current working values in, and a direct conceptual ancestor of the 6-transistor SRAM cell used to build cache memory.

Key takeaways

• A half-adder is one XOR gate (Sum) plus one AND gate (Carry); a full adder chains half-adders to handle carry-in, and chaining full adders builds a multi-bit binary adder.
• Combinational logic (like an adder) has no memory — output depends only on current input.
• Feeding a gate’s output back into its own input (as in the SR latch) creates sequential logic that can hold a bit indefinitely.
• Real chips use clocked flip-flops, which update only on a clock edge, to build reliable registers — a stepping stone to SRAM and to the chip design flow that turns these ideas into silicon.