Logic Gates

A logic gate is a tiny decision-maker: it looks at one or two input bits and instantly outputs a new bit based on a fixed rule. Wire enough of these simple decision-makers together — billions of them, in fact, on a modern processor — and you get something that can play video, run a spreadsheet, or fly a rocket. Every one of those billions of gates, though, boils down to a handful of basic types you can fully understand in a few minutes.

The basic gates

The three simplest gates are AND, OR, and NOT. Each has a standard symbol and a truth table — a complete listing of every possible input combination and the output it produces.

AND outputs 1 only when both inputs are 1. OR outputs 1 when at least one input is 1. NOT simply flips its single input — it’s also called an inverter, a name you’ll see again in the CMOS logic page.

The derived gates: NAND, NOR, XOR

Three more gates come from combining the basics: NAND (“NOT AND”), NOR (“NOT OR”), and XOR (“exclusive OR”).

NAND is just AND with the output flipped; NOR is OR with the output flipped. XOR outputs 1 only when its inputs disagree — it’s the “exactly one of these, not both” gate, and it turns out to be exactly the circuit you need to add two bits together (see From Gates to Circuits).

In boolean algebra, using $\cdot$ for AND, $+$ for OR, and an overbar for NOT, XOR is written:

This reads as: “A XOR B is true when A is true and B is false, OR A is false and B is true” — in other words, when exactly one input is 1.

Why NAND and NOR are “universal”

Here’s a fact that surprises a lot of people the first time they hear it: you can build every single one of the gates above — AND, OR, NOT, XOR, anything — using nothing but copies of a single NAND gate (or, alternatively, nothing but NOR gates). That’s why NAND and NOR are called universal gates.

    flowchart LR
    A1["A"] --> N1["NAND"]
    A1 --> N1
    N1 --> NOT_out["NOT A<br/>(tie both inputs together)"]

    B1["A"] --> N2["NAND"]
    B2["B"] --> N2
    N2 --> N3["NAND"]
    N2 --> N4["NAND"]
    N3 --> N5["NAND"]
    N4 --> N5
    N5 --> AND_out["A AND B"]
  

The practical reason this matters: chip manufacturers can design, test, and optimize one extremely efficient physical circuit for a NAND gate (you’ll see exactly how it’s built from transistors in CMOS logic), then stamp out billions of copies and wire them together to build any logical function at all. It simplifies both the manufacturing process and the automated tools that convert a chip designer’s high-level intent into physical transistors.

Combining gates into expressions

Real digital circuits chain gates together into networks. For example, the expression $Y = (A \cdot B) + \bar{C}$ describes a small circuit: feed A and B into an AND gate, feed C into a NOT gate, then feed both of those outputs into an OR gate. Chip designers rarely draw every single gate by hand at this level for a modern processor — instead they write these relationships in a hardware description language, but the underlying logic is exactly this kind of gate composition, all the way down.

Key takeaways

• AND, OR, and NOT are the three fundamental logic gates, each defined by a simple truth table.
• NAND, NOR, and XOR are built from combinations of the basics; XOR is the “exactly one input is 1” gate.
• NAND and NOR are each “universal” — any logic function can be built from either one alone, which is why real chips are built almost entirely out of NAND (or NOR) cells.
• Gates take voltage-encoded bits as inputs and outputs, and physically they’re built from MOSFETs, covered next in CMOS Logic.