Metallization and Interconnects

A modern chip can have tens of billions of transistors, and every single one of them is useless in isolation — it has to be wired to exactly the right neighbors to form a working circuit. Metallization is the process of building that wiring: not one layer of wires, but a genuine 3D stack of ten, fifteen, sometimes twenty-plus layers of metal, each one connecting to the layer above and below through microscopic vertical plugs.

Why wiring needs its own multi-layer stack

Transistors are built at the very bottom of the chip, packed as densely as possible in two dimensions. But a real circuit needs signals to travel between transistors that can be far apart, needs power and ground distributed evenly across the entire chip, and needs to do all of this without any wire ever touching another wire it isn’t supposed to. There simply isn’t enough room to route every connection in a single flat layer — so chips build wiring upward instead, in layers separated by insulation, similar to how a multi-level highway interchange uses overpasses and underpasses to let traffic going in different directions cross without colliding.

The metal layer stack

    flowchart TD
    A["Transistors<br/>(front-end-of-line)"] --> B["Contacts<br/>(connect transistor to metal)"]
    B --> C["Metal 1 (M1)<br/>densest, narrowest wires"]
    C --> D["Via 1<br/>vertical connector"]
    D --> E["Metal 2 (M2)"]
    E --> F["... more metal/via pairs ..."]
    F --> G["Upper metal layers<br/>wider, for power/long-range signals"]
    G --> H["Top-level pads<br/>for external connections"]
  

Lower metal layers (closest to the transistors) use the thinnest, most tightly packed wires, matching the fine pitch of the transistors themselves. As layers go up, wires get progressively wider and more widely spaced, because they need to carry more current with less resistance and route signals across longer distances — exactly like local streets feeding onto progressively bigger roads and highways.

Why copper, and the damascene process

Aluminum wiring dominated chips through the 1990s, but modern chips almost universally use copper for these interconnects, because copper conducts electricity with roughly 40% less resistance than aluminum — meaning signals move faster and less energy is wasted as heat, both of which matter enormously once you have billions of transistors switching billions of times per second.

This is the basic resistance formula for any wire: $R$ is resistance, $\rho$ (rho) is the resistivity of the metal (lower for copper than aluminum), $L$ is the wire’s length, and $A$ is its cross-sectional area. As transistors shrink, wires must shrink too, which shrinks $A$ and drives $R$ up — a real problem, since higher wire resistance combined with the capacitance between neighboring wires (the “RC” in RC delay) slows down how fast a signal can travel, sometimes more than the transistors themselves have improved. Choosing a lower-resistivity metal like copper, and using low-k dielectric to cut capacitance, are two of the main tools engineers have to fight this effect.

There’s a catch: copper is difficult to etch precisely with the plasma techniques covered in Etching and Deposition, and copper atoms diffuse into (contaminate) silicon and disrupt transistor behavior if not carefully contained. The industry’s solution is the damascene process, named after an ancient metal-inlay technique:

1. Etch trenches and vias into an insulating layer (rather than etching the metal itself) — the trench shapes are the wire pattern for this layer, the vias are the vertical holes down to the layer below.
2. Deposit a thin barrier layer (often tantalum nitride) lining the trenches and vias, which stops copper atoms from diffusing into the surrounding insulator or down toward the transistors.
3. Deposit a thin copper seed layer by PVD, then electroplate bulk copper to completely fill the trenches and vias and overflow onto the whole wafer surface.
4. Chemical-Mechanical Planarization (CMP) polishes away all the excess copper sitting above the trenches, leaving copper only inside the etched trenches and vias — flush with the insulating surface, ready for the next layer.

This is often called dual damascene, since a single fill-and-polish cycle simultaneously forms both the horizontal wire (trench) and the vertical via connecting down to the previous layer.

Cross-section of a multi-layer copper stack

The insulating material between and around the copper wires is a low-k dielectric — an insulator specifically engineered to have a low dielectric constant, which reduces unwanted capacitance (and therefore signal delay and power loss) between neighboring wires packed this closely together.

Key takeaways

• Metallization builds the multi-layer wiring stack that connects billions of transistors, using progressively wider, more widely spaced wires from bottom to top.
• Copper replaced aluminum for its lower resistance, but requires the damascene process — etching trenches into insulator, lining them with a diffusion barrier, filling with electroplated copper, and polishing flat with CMP — because copper is hard to etch directly.
• Vias are the vertical connectors linking one metal layer to the next; dual damascene forms a trench and via together in one fill-and-polish cycle.
• Low-k dielectric insulation between wires reduces capacitance, keeping signals fast and power loss low as wires get packed closer together.

For how these layers eventually get diced apart and packaged, see Packaging and Testing. For how the whole layered structure gets designed in the first place, see Design Flow: RTL to GDSII.