Packaging and Testing

A finished wafer, fresh out of the fab, isn’t a chip you can plug into anything — it’s a fragile disk covered in hundreds of tiny, delicate circuits with no way to connect to the outside world and no protection from dust, moisture, or a stray fingernail. Packaging and testing is the final stretch: cutting that wafer into individual chips, wiring each one into a protective housing, and proving — electrically, not just visually — that it actually works before it’s allowed to ship.

From wafer to individual dies

Before any cutting happens, every single die on the wafer is electrically probed while still attached to the wafer, using an array of tiny needle-like probes that touch each die’s test pads. This step, called wafer probing (or wafer sort), runs a battery of electrical tests on each individual die and marks bad ones — often literally, with a drop of ink in older fabs, or more commonly today in a digital wafer map — so they can be skipped later. Only after probing does the wafer get diced: cut apart, almost always today with a precision diamond saw or a laser, along narrow un-patterned strips called scribe lines, separating the wafer into hundreds or thousands of individual chips (“dies”).

🧩 Think of it like… a sheet of stickers. The wafer is the whole sheet, each die is one sticker, and the scribe lines are the perforations between them. Before you tear any sticker off, you check the whole sheet for smudged or misprinted ones and mark them — no point wasting effort packaging a chip you already know is broken.

    flowchart TD
    A["Finished wafer"] --> B["Wafer probing<br/>(electrical test per die)"]
    B --> C["Wafer map:<br/>good vs. bad dies marked"]
    C --> D["Dicing<br/>(saw or laser cut)"]
    D --> E["Good dies selected"]
    E --> F["Die attach<br/>(mount die to package)"]
    F --> G["Electrical connection:<br/>wire bond or flip-chip"]
    G --> H["Encapsulation<br/>(mold compound / lid)"]
    H --> I["Final test and burn-in"]
    I --> J["Binning by speed/power"]
    J --> K["Marked, shipped chip"]

Connecting the die: wire bonding vs. flip-chip

A bare die has a ring or grid of tiny metal pads on its top surface — the very endpoints of the interconnect stack described in Metallization and Interconnects. Those pads need to be electrically connected to the metal pins or balls on the outside of the package. There are two dominant approaches:

Wire bonding — the die is mounted face-up in the package, and extremely thin wires (usually gold, copper, or aluminum, often thinner than a human hair) are bonded one at a time from each pad on the die’s edge to a corresponding pin on the package frame. It’s a mature, low-cost, and reliable technique, but it only connects pads around the die’s perimeter, and each wire adds a small amount of electrical resistance and inductance that limits high-speed signals.
Flip-chip — the die is flipped face-down, with small solder or copper “bumps” pre-formed directly on its pads, and those bumps are reflowed (melted briefly) to bond directly onto matching pads on the package substrate. This allows connections across the die’s entire face rather than just the edges, supporting far more connections and much shorter, faster electrical paths — essential for high-performance processors — at higher manufacturing cost.

Wire bondingpackage substratediedie face-up,wires loop to package edge

Flip-chippackage substratedie (flipped)die face-down,solder bumps across whole face

Encapsulation and common package types

Once electrically connected, the die and its connections are protected — most commonly by injecting a hardened epoxy mold compound around the whole assembly, or in some high-performance or hermetic applications, sealing it under a metal or ceramic lid. Some familiar package families:

QFP (Quad Flat Package) — a square package with thin metal legs extending from all four sides, commonly wire-bonded, widely used for low-to-medium pin-count chips.
BGA (Ball Grid Array) — instead of legs around the edge, an entire grid of small solder balls covers the underside of the package, allowing far more connections in the same footprint; commonly paired with flip-chip die attachment for high pin-count, high-performance chips.
Chip-scale and advanced packages — packages barely larger than the die itself, or multiple dies stacked or placed side-by-side in one package (see Chiplets and 3D Packaging for how far this idea now extends).

Final test and binning

Even after wafer probing caught the obviously broken dies, packaged chips go through a full final test: every function is exercised at multiple voltages, temperatures, and clock speeds, sometimes after a stress step called burn-in that runs the chip hard for a period to catch parts that would fail early in the field (“infant mortality” failures). Chips that pass are often binned — sorted into different product tiers based on the maximum speed or lowest power they can reliably achieve, since manufacturing variation means not every chip from the same design performs identically. This is a major reason a manufacturer can sell what is physically the same design as several different product models at different price points.

\text{Final yield} = Y_{\text{wafer probe}} \times Y_{\text{assembly}} \times Y_{\text{final test}}

Each $Y$ term is the fraction of dies surviving that stage (a value between 0 and 1). Multiplying them together gives the overall fraction of dies that started on the wafer and made it all the way to a shippable, working chip — the number that ultimately determines how much each good chip actually costs to produce.

Catching a defect earlier is always cheaper. A die that fails wafer probing costs almost nothing extra to discard — but a die that fails only after full packaging has already consumed the cost of dicing, bonding, and encapsulation. That’s the whole economic reason wafer probing happens before dicing rather than skipping straight to final test.

Key takeaways

Wafer probing electrically tests every die while still on the wafer, before dicing, so obviously bad dies are never wasted on packaging.
Dicing cuts the wafer into individual dies along scribe lines, usually with a saw or laser.
Wire bonding connects a face-up die’s edge pads with fine wires; flip-chip flips the die and uses solder bumps across its whole face for more connections and shorter, faster paths.
Final test (and often burn-in) after encapsulation catches remaining defects and bins chips into product tiers by achieved speed and power.

Metallization and Interconnects