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DRAM

DRAM

Every gigabyte of “RAM” in your laptop or phone’s main memory spec sheet is DRAM (Dynamic Random-Access Memory) — and the reason it can be so cheap and so dense, packing billions of bits onto a small chip, is that each bit is stored in the simplest possible circuit: just one transistor and one capacitor. The catch is right there in the name: it’s dynamic, meaning the stored charge constantly leaks away and has to be topped up thousands of times per second or the data is lost.

The 1T1C cell

Each DRAM bit is stored as an electric charge sitting on a tiny capacitor — think of it as a microscopic bucket that can hold electrons. A single access transistor acts as a gate to that bucket: when its word line is raised, the transistor connects the capacitor to a bit line, letting the outside world either dump charge in (write a 1), drain it out (write a 0), or measure how much is there (read the bit).

1-Transistor 1-Capacitor DRAM CellBLAccesstransistorWLCapacitor(charge = bit)other plate tied to a fixed reference voltagecharge leaksaway over time
🧩 Think of it like… a tiny paper cup of water (the capacitor) representing a "1" when full and a "0" when empty, with a valve (the transistor) controlling access to it. The trouble is, paper cups leak — water seeps out slowly no matter what you do. If nobody ever comes back to top off a "full" cup, it eventually looks just as empty as a "0" cup, and the information is lost. So every cup has to be revisited and refilled, over and over, thousands of times a second, whether or not anyone's actually reading from it.

Why it needs refreshing

A capacitor is not a perfect vault — its charge inevitably leaks away through tiny imperfect insulation and through the access transistor itself, even while it’s switched off. Left alone, a “1” would gradually drift down toward “0” and become unreadable within a matter of milliseconds. To prevent this, a DRAM controller performs a refresh operation: it periodically reads each row of cells and immediately writes the same value straight back, restoring the charge to full strength before it decays too far to distinguish from a 0.

trefresh=tREFNrowst_{refresh} = \frac{t_{REF}}{N_{rows}}

A typical DRAM chip specifies a full-array refresh interval tREFt_{REF} of around 64 milliseconds, during which every row (of, say, 8,192 rows, NrowsN_{rows}) must be refreshed once. That works out to roughly 64ms/8192≈7.8 μs64\text{ms} / 8192 \approx 7.8\ \mu s between individual row refreshes — a constant, largely invisible background task the memory controller performs continuously, even when the computer is otherwise idle, which is part of why DRAM burns a small but nonzero amount of power just sitting there holding data.

Reading a DRAM cell is itself destructive — pulling charge out onto the bit line to sense it also drains the capacitor. That’s why every DRAM read is immediately followed by a write-back of the same value, quietly folding a “refresh” into the read operation itself.

Why it’s dense, cheap, and the default for main memory

Compared to SRAM’s six transistors per bit, DRAM’s single transistor plus a compact capacitor lets manufacturers pack vastly more bits into the same silicon area — which is exactly why your main memory is measured in gigabytes while your CPU cache is measured in megabytes. The tradeoff is speed and complexity: DRAM access is slower than SRAM (the capacitor must be sensed and immediately refreshed on every read) and requires that constant background refresh machinery. That’s the fundamental engineering trade running through all of memory design — SRAM trades density for speed and simplicity, DRAM trades speed for density and cost.

Key takeaways

  • A DRAM cell stores one bit as charge on a capacitor, accessed through a single transistor gated by a word line.
  • Capacitor charge leaks away over time, so DRAM must be periodically refreshed — reading a row and writing its value straight back — typically within tens of milliseconds per row.
  • Reading a DRAM cell is destructive, so every read is paired with a write-back that doubles as a refresh.
  • One transistor and one capacitor per bit makes DRAM far denser and cheaper than SRAM, which is why DRAM is used for main memory while SRAM is reserved for cache.
SRAMNAND Flash