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SRAM

SRAM

Somewhere on every processor is a small pool of memory so fast it can keep up with the CPU’s core running at full speed — that’s SRAM (Static Random-Access Memory), used to build the L1/L2/L3 cache that sits between the processor and main memory. It’s also the most expensive memory per bit, because each single bit takes six transistors to store, and it’s a beautifully direct application of the feedback trick from From Gates to Circuits.

The 6-transistor cell

An SRAM cell is built from two CMOS inverters cross-coupled — the output of each feeds the input of the other, exactly like the SR latch you saw earlier, just built from inverters instead of NOR gates. That loop, on its own, is a bistable circuit: it settles into one of exactly two stable states (Q=1/Q̄=0, or Q=0/Q̄=1) and stays there indefinitely as long as power is applied. Two more transistors, called access transistors, connect the loop to the outside world only when a word line is activated, letting a bit line pair read or write the stored value.

6-Transistor SRAM CellInverter 1Inverter 2QQ̄AccessAccessWLBLBL̄

4 transistors (2 inverters) hold the bit; 2 accesstransistors connect it to the bit lines when WL is high

🧩 Think of it like… two people arguing, each one shouting the exact opposite of whatever the other just said. Left alone, they'll settle into a stable back-and-forth — one always says "yes," the other always says "no" — and they'll keep doing it forever without anyone reminding them. To find out which one is currently saying "yes," you just open a door (the access transistor) and listen; you don't have to interrupt or restart their argument to read it.

Reading and writing

To read a bit, the word line is raised, connecting both inverter outputs to the bit line pair. Sensing circuitry outside the cell detects a tiny voltage difference between BL and BL̄ and amplifies it into a clean 0 or 1. To write a bit, external drivers force strong opposite voltages onto BL and BL̄ while the word line is raised — strong enough to overpower the cell’s own feedback loop and flip it into the new state, after which the loop happily holds the new value on its own.

Why SRAM is fast, big, and power-hungry — but needs no refresh

Because the stored bit lives in an active feedback loop of transistors rather than in a leaky capacitor, SRAM has one major advantage over its counterpart DRAM: it is static — it holds its value as long as power is supplied, with no periodic refresh required, hence the name. That stability, combined with the fact that reading doesn’t disturb the stored value, is what makes SRAM fast enough to keep pace with a CPU core running at multiple gigahertz.

The cost is size and power: six transistors per bit is a lot of silicon area compared to DRAM’s one transistor and one capacitor, so SRAM is far more expensive per bit and used sparingly — for the small, blazing-fast cache tiers, not for a computer’s multi-gigabyte main memory pool.

Areacell≈6×Areatransistor\text{Area}_{cell} \approx 6 \times \text{Area}_{transistor}

This rough relationship is why cache capacity on a chip is measured in kilobytes to a few tens of megabytes, while main memory (built from DRAM) is measured in gigabytes on the very same manufacturing process.

Key takeaways

  • An SRAM cell is two cross-coupled CMOS inverters (4 transistors) plus 2 access transistors gated by a word line, connecting to a bit line pair.
  • The cross-coupled loop is bistable — it holds one of two stable states indefinitely with power applied, needing no refresh.
  • Six transistors per bit makes SRAM large and costly per bit, but its speed and stability make it the standard choice for CPU cache.
  • Compare this directly with DRAM, which trades SRAM’s stability for a much smaller, cheaper cell that must be periodically refreshed.
DRAM